CEA-Leti has announced a new collaboration with Intel on 3D packaging technologies for processors to advance chip design. The research will focus on assembly of smaller chiplets, optimizing interconnection technologies between the different elements of microprocessors, and on new bonding and stacking technologies for 3D ICs, especially for making high performance computing (HPC) applications.
3D technology, which stacks chips vertically in a device, not only optimizes the power of the chip with advanced packaging interconnects between components, but it also allows the creation of heterogeneous integration of chiplets. That ultimately allows fabrication of more efficient, thinner and lighter microprocessors. In addition, by implementing multiple heterogeneous solutions in a single package, chip companies benefit from considerable flexibility, such as mixing and matching different technology blocks with different IP and integrating memory and input / output technologies within the same component. This enables chip makers to continue to innovate and adapt to the needs of their customers and partners.
The key to the work being done by CEA-Leti is to develop new 3D bonding and stacking technologies for integration of devices manufactured in different processes. Speaking to EE Times, Severine Cheramy, the 3D business development director at CEA-Leti, explained the collaboration with Intel is focused on advanced technologies to increase the density of interconnects, and hence decrease the pitch. When asked about the expected outcome of the collaboration, she said she was unable to disclose specific details, but that “we together define a scope of work, technical objectives and deliverables.” She said typically the deliverables might include a technical report and/or some wafers.
Speaking more broadly about the challenges for 3D packaging, she said more advanced research is needed to address issues like production difficulty or simply addressing the cost of implementation. She added, “This collaboration is proof that the electronics world is moving towards advanced packaging and chiplets, and we have some working technology in design flow and test. At a higher level, all the key players working on these advanced packaging technologies need to continue to work together on standardization of interfaces, given that different chiplets from different companies will have different interfaces.”
In 2019, Intel introduced a 3D-stacking technology, Foveros, that adapted these design features. This advanced-packaging technology, launched in Intel Core processors with Intel hybrid technology (codenamed Lakefield), comes in a small physical package for significantly reduced board size to offer an optimal balance between performance and energy efficiency. At the IEEE Electronic Components and Technology Conference in June 2020, CEA-Leti received the best paper award for its work, carried out at IRT Nanoelec, on silicon active interposer as a promising solution towards 3D heterogeneous integration.
Earlier this year, at ISSCC 2020 in February, CEA-Leti presented a paper highlighting its breakthrough in active interposer and 3D stacked chiplets, “A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2 @ 82%-Peak-Efficiency DC-DC Converters.”
Its prototype highlighted in the paper offers a modular and energy-efficient integration platform to enable efficient integration of large-scale chiplet-based computing systems such as high-performance computing (HPC) and big-data applications.
While large-scale interposer techniques for chiplet integration have previously been fabricated using various technologies, such as 2.5D passive interposers, organic substrates, and silicon bridges, these technologies lacked flexible long-distance chiplet-to-chiplet communications to connect a larger number of chiplets. They also lack smooth integration of heterogeneous chiplets, and the easy integration of less-scalable functions such as tightly coupled power-management solutions, analog functions and IO IPs.
This is what CEA-Leti is addressing, under the framework of IRT Nanoelec, to overcome these limitations by introducing an active-interposer technology that enables integration of some active CMOS circuitry on a large-scale interposer. They also managed its implementation on a STMicroelectronics process using a 3D CAD tool design flow from Mentor Graphics, a Siemens business.
The active interposer integrates:
- voltage regulators fully integrated without passives for efficient power management of the 3D-stacked chiplets
- flexible system interconnect topologies between all chiplets for scalable cache-coherency support
- energy-efficient 3D-plugs for dense high-throughput, inter-layer communication, and
- a memory-IO controller and the physical layer (PHY) for socket communication.
The prototype’s 96 computing cores are organized in six chiplets in 28nm FDSOI, CMOS node, which are 3D-stacked in a face-to-face configuration using 20µm pitch micro-bumps onto an active interposer embedding through-silicon vias (TSVs) in a 65nm technology node. The overall system architecture offers a fully scalable distributed cache-coherent architecture between all the chiplet computing tiles, which are interconnected through the active interposer. The innovative cache-coherent architecture allows easy software deployment through a hierarchy of caches, for full system scalability up to 512 cores.
Future work will address die-to-wafer hybrid bonding technology, which offers denser 3D interconnects with better electrical, mechanical and thermal parameters, and allows ultra-dense, low-energy parallel interfaces. For the longer term, CEA-Leti is also investigating innovative photonic-interposer technology as a 3D-based photonic chiplet approach, offering low-latency, high-bandwidth, energy-efficient photonic communication.
